I/O Devices

Hierarchical System Architecture

The CPU sits next to main memory on a short, proprietary high-speed interconnect. Latency-sensitive parts such as a graphics card attach to a general I/O fabric (PCI Express). Disks, keyboards and mice live on cheaper, longer peripheral buses (SATA, USB). Physics forces faster buses to be short, and those buses are expensive to design, so slower, numerous devices are placed farther away.

Canonical Device Makeup

A device presents a handful of registers to software: a status register that reports idle or busy, a command register that accepts an opcode, and a data register used to move bytes in or out. Internally the device contains a microcontroller, SRAM or DRAM, and special-purpose silicon; sophisticated units even run tens of thousands of lines of firmware. The operating system only needs to honour the published interface.

Polling Interaction Protocol

Software repeatedly reads the status register until the device is idle, copies bytes into the data register (CPU-driven movement called programmed I/O), writes a command that starts the hardware, then polls again until the operation finishes. The sequence is simple and reliable, yet the two busy-wait loops leave the processor spinning, which is especially costly when the device itself is slow.

Interrupts Cut Processor Overhead

After launching a request the operating system puts the calling process to sleep and switches to another ready task. When the device finishes it asserts a hardware interrupt; the processor vectors into a registered handler that collects results or an error code and then wakes the waiter. Computation and I/O therefore overlap instead of the processor spinning.

Pitfalls

• Continuous polling of a slow device can drive CPU utilisation near zero.
• Forgetting to inspect the error bits in the status register after a command finishes can cause silent data corruption.
• Moving large buffers with programmed I/O turns the processor into a copy engine; DMA should be used instead.

Minimum C11 · complete program · Download .c

#include <stdio.h>

int main(void) {
    printf("=== Simulating Canonical I/O Protocol ===\n");
    printf("Step 1: OS polls STATUS register until not BUSY\n");
    printf("  (in reality this loop wastes CPU)\n");
    printf("Step 2: OS writes data to DATA register (PIO)\n");
    printf("Step 3: OS writes command to COMMAND register\n");
    printf("Step 4: OS polls STATUS until complete\n");
    printf("I/O done. Using interrupts would overlap this wait with other computation.\n");
    return 0;
}

Compile locally

gcc -std=c11 -Wall -Wextra -Wpedantic -Werror ostep-36-io-devices.c -o example && ./example

Expected result

=== Simulating Canonical I/O Protocol ===
Step 1: OS polls STATUS register until not BUSY
  (in reality this loop wastes CPU)
Step 2: OS writes data to DATA register (PIO)
Step 3: OS writes command to COMMAND register
Step 4: OS polls STATUS until complete
I/O done. Using interrupts would overlap this wait with other computation.

CHECK YOUR UNDERSTANDING

Close the answer. Explain it.

Why does a machine not attach every device directly to the high-speed memory interconnect, instead using a hierarchy of buses?

Check the sources

• OSTEP chapter PDF

Drafts and official chapters change. The version mark is only the example’s minimum.